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  the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd77110, 77111, 77112 16-bit fixed-point digital signal processors document no. u12801ej4v0ds00 (4th edition) date published november 1999 n cp(k) printed in japan data sheet the mark shows major revised points. 1998, 1999 description the m pd77110, 77111, and 77112 are 16-bit fixed-point digital signal processors (dsps). compared with the m pd77016 family, these dsps have improved power consumption and are ideal for battery- powered mobile terminals such as pdas and cellular phones. both mask rom and ram models are available. for details of the functions of these dsps, refer to the following users manuals: m pd77111 family users manual : to be available soon m pd7701x family users manual - instructions: u13116e features z instruction cycle (operating clock) m pd77110 : 15.3 ns min (65 mhz max) 13.3 ns min (75 mhz max) (operating voltage and ambient temperature are limited.) m pd77111 : 13.3 ns min (75 mhz max) m pd77112 : 13.3 ns min (75 mhz max) z memory ? internal instruction memory m pd77110 : ram 35.5k words 32 bits m pd77111 : ram 1k words 32 bits mask rom 31.75k words 32 bits m pd77112 : ram 1k words 32 bits mask rom 31.75k words 32 bits ? data memory m pd77110 : ram 24k words 16 bits 2 banks external memory space 32k words 16 bits 2 banks m pd77111 : ram 3k words 16 bits 2 banks mask rom 16k words 16 bits 2 banks m pd77112 : ram 3k words 16 bits 2 banks mask rom 16k words 16 bits 2 banks external memory space 16k words 16 bits 2 banks
data sheet u12801ej4v0ds00 2 m m m m pd77110, 77111, 77112 ordering information part number package m pd77110gc-9eu 100-pin plastic tqfp (fine pitch) (14 14 mm) m pd77111gk-xxx-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd77111f1-xxx-cn1 80-pin plastic fine-pitch bga (9 9 mm) m pd77112gc-xxx-9eu 100-pin plastic tqfp (fine pitch) (14 14 mm) remark xxx indicates rom code suffix.
data sheet u12801ej4v0ds00 3 m m m m pd77110, 77111, 77112 block diagram serial i/o #1 peripheral units data memory unit operation unit program control unit serial i/o #2 port host i/o x memory data addressing unit x memory y memory interrupt control loop control stack pc stack pll mpy 16 ? 16 + 40 40 alu (40) r0 - r7 x bus y bus external memory int1 - int4 note 1 reset clkout clkin wakeup note 1 pll0 - pll2 note 2 main bus wait controller ie i/o cpu control notes 1. the wakeup pin is multiplexed with the int4 pin. with the pd77111 and 77112, the function of the wakeup pin can be activated or deactivated by mask option. with the pd77110, this function is always valid. 2. these pins are provided only on the pd77110. the pll0 and pll1 pins are multiplexed with the p2 and p3 pins. bsft y memory data addressing unit instruction memory m m m
data sheet u12801ej4v0ds00 4 m m m m pd77110, 77111, 77112 pin configuration +2.5 v +3 v iv dd ev dd reset, interrupt system control data bus control clock external data memory serial interface #1 serial interface #2 host interface port for debugging (4) (4) (3) (15) (16) (2) (4) (2) (8) so1 sorq1 soen1 sck1 si1 sien1 siak1 reset int1 - int4 clkin clkout pll0 - pll2 note 1 wakeup note 2 da0 - da14 note 3 x/y d0 - d15 mrd mwr holdrq holdak bstb so2 soen2 sck2 si2 sien2 hcs ha0, ha1 hrd hre hwr hwe hd0 - hd7 tdo, tice tck, tdi, tms, trst p0 - p3 gnd note 4 notes 1. these pins are provided only on the m pd77110. 2. with the m pd77111 and 77112, the function of this pin can be activated or deactivated by mask option. with the m pd77110, this function is always valid. 3. da14 is not provided on the m pd77112. 4. an external data memory interface is not provided on the m pd77111.
data sheet u12801ej4v0ds00 5 m m m m pd77110, 77111, 77112 item pd77016 mm m mm m m pd77019 pd77018a pd77019-013 pd77111 pd77112 mm pd77113 pd77114 memory space (words bits) instruction cycle (at maximum speed) multiple serial interface (two channels) supply voltage package internal instruction ram internal instruction rom data ram (x/y memory) data rom (x/y memory) external data memory (x/y memory) external instruction memory 1.5k 32 256 32 4k 32 1k 32 24k 32 none none 31.75k 32 2k 16 each 3k 16 each 3k 16 each none 12k 16 each 16k 16 each 48k 32 5 v 3 v dsp core: 2.5 v i/o pins : 3 v 160-pin qfp none 48k 16 each 16k 16 each none 16k 16 each 30 ns (33 mhz) 100-pin tqfp 80-pin tqfp 80-pin fbga 100-pin tqfp 100-pin tqfp 116-pin bga 1, 2, 3, 4, 8 (mask option) fixed to 4 integer of 1 to 16 (mask option) 16.6 ns (60 mhz) 13.3 ns (75 mhz) channels 1 and 2 have same function. channel 1 has same function as pd77016. channel 2 does not have sorq2 and siak2 pins (for connection of codec). m pd77110 35.5k 32 24k 16 each 32k 16 each 15.3 ns (65 mhz) integer of 1 to 8 (external pin) none 3.5k 32 48k 32 16k 16 each 32k 16 each none 8k 16 each 80-pin fbga 100-pin tqfp dsp function list
data sheet u12801ej4v0ds00 6 m m m m pd77110, 77111, 77112 pin configuration 100-pin plastic tqfp (fine-pitch) (14 14 mm) (top view) m m m m pd77110gc-9eu m m m m pd77112gc-xxx-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 gnd da14/nc note 1 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 d15 d14 d13 d12 d11 d10 d9 d8 ev dd ev dd clkin clkout ha1 ha0 hwr hrd hcs hwe hre gnd ev dd hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 p0 p1 p2/pll0 note 4 p3/pll1 note 3 gnd ev dd x/y i.c. mrd mwr nu bstb holdak holdrq int1 int2 int3 int4/wakeup note 5 reset gnd iv dd trst tms tdi tck tice tdo gnd iv dd gnd gnd d7 d6 d5 d4 d3 d2 d1 d0 iv dd gnd si1 sien1 sck1 siak1 so1 sorq1 soen1 soen2 so2 sck2 sien2 si2 pll2/nc note 2 ev dd 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 notes 1. da14 with m pd77110, nc with m pd77112 2. pll2 with m pd77110, nc with m pd77112 3. p3 only for m pd77112 4. p2 only for m pd77112 5. with the m pd77112, the function of the wakeup pin can be activated or deactivated by a mask option.
data sheet u12801ej4v0ds00 7 m m m m pd77110, 77111, 77112 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 gnd 26 gnd 51 gnd 76 gnd 2 da14/nc 27 d7 52 p3/pll1 77 iv dd 3 da13 28 d6 53 p2/pll0 78 gnd 4 da12 29d5 54p1 79tdo 5 da11 30d4 55p0 80tice 6 da10 31d3 56hd7 81tck 7 da9 32 d2 57 hd6 82 td1 8 da8 33 d1 58 hd5 83 tms 9 da7 34 d0 59 hd4 84 trst 10 da6 35 iv dd 60 hd3 85 iv dd 11 da5 36 gnd 61 hd2 86 gnd 12 da4 37 si1 62 hd1 87 reset 13 da3 38 sien1 63 hd0 88 int4/wakeup 14 da2 39 sck1 64 ev dd 89 int3 15 da1 40 siak1 65 gnd 90 int2 16 da0 41 so1 66 hre 91 int1 17 d15 42 sorq1 67 hwe 92 holdrq 18 d14 43 soen1 68 hcs 93 holdak 19 d13 44 soen2 69 hrd 94 bstb 20 d12 45 so2 70 hwr 95 nu 21 d11 46 sck2 71 ha0 96 mwr 22 d10 47 sien2 72 ha1 97 mrd 23 d9 48 si2 73 clkout 98 i.c. 24 d8 49 pll2/nc 74 clkin 99 x/y 25 ev dd 50 ev dd 75 ev dd 100 ev dd
data sheet u12801ej4v0ds00 8 m m m m pd77110, 77111, 77112 80-pin plastic tqfp (fine-pitch) (12 12 mm) (top view) m m m m pd77111gk-xxx-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 gnd nu nu nu nu nu nu nu nu ev dd gnd nu nu nu nu nu nu nu nu ev dd ev dd clkout ha1 ha0 hwr hrd hcs hwe hre gnd ev dd hd0 hd1 hd2 hd3 hd4 hd5 hd6 hd7 gnd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 gnd si1 sien1 sck1 siak1 so1 sorq1 soen1 soen2 so2 iv dd gnd sck2 sien2 si2 p3 p2 p1 p0 ev dd ev dd nu nu int1 int2 int3 int4/wakeup reset gnd iv dd trst tms tdi tck tice tdo gnd iv dd clkin gnd
data sheet u12801ej4v0ds00 9 m m m m pd77110, 77111, 77112 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 gnd 21 gnd 41 gnd 61 gnd 2 nu 22 si1 42 hd7 62 clkin 3 nu 23 sien1 43 hd6 63 iv dd 4 nu 24 sck1 44 hd5 64 gnd 5 nu 25 siak1 45 hd4 65 tdo 6 nu 26 so1 46 hd3 66 tice 7 nu 27 sorq1 47 hd2 67 tck 8 nu 28 soen1 48 hd1 68 tdi 9 nu 29 soen2 49 hd0 69 tms 10 ev dd 30 so2 50 ev dd 70 trst 11 gnd 31 iv dd 51 gnd 71 iv dd 12 nu 32 gnd 52 hre 72 gnd 13 nu 33 sck2 53 hwe 73 reset 14 nu 34 sien2 54 hcs 74 int4/wakeup note 15 nu 35 si2 55 hrd 75 int3 16 nu 36 p3 56 hwr 76 int2 17 nu 37 p2 57 ha0 77 int1 18 nu 38 p1 58 ha1 78 nu 19 nu 39 p0 59 clkout 79 nu 20 ev dd 40 ev dd 60 ev dd 80 ev dd note the function of the wakeup pin can be activated or deactivated by a mask option.
data sheet u12801ej4v0ds00 10 m m m m pd77110, 77111, 77112 80-pin plastic fine-pitch bga (9 9 mm) m m m m pd77111f1-xxx-cn1 (bottom view) (top view) jhgfedcba abcdefghj 9 8 7 6 5 4 3 2 1 index mark pin no. pin name pin no. pin name pin no. pin name pin no. pin name a1 ev dd c3 nu e6 hre g8 hd4 a2 nu c4 reset e7 hd0 g9 hd5 a3 int2 c5 trst e8 gnd h1 nu a4 int4/wakeup note c6 tice e9 ev dd h2 nu a5 iv dd c7 clkin f1 nu h3 sien1 a6 tck c8 ha0 f2 nu h4 soen1 a7 iv dd c9 hwr f3 nu h5 gnd a8 gnd d1 nu f4 siak1 h6 si2 a9 ev dd d2 nu f5 soen2 h7 p1 b1 nu d3 nu f6 p2 h8 gnd b2 gnd d4 int1 f7 hd1 h9 hd7 b3 nu d5 tms f8 hd3 j1 ev dd b4 int3 d6 tdo f9 hd2 j2 gnd b5 gnd d7 hcs g1 nu j3 sck1 b6 tdi d8 hrd g2 nu j4 sorq1 b7 gnd d9 hwe g3 si1 j5 iv dd b8 clkout e1 ev dd g4 so1 j6 sck2 b9 ha1 e2 gnd g5 so2 j7 p3 c1 nu e3 nu g6 sien2 j8 p0 c2 nu e4 nu g7 hd6 j9 ev dd note the function of the wakeup pin can be activated or deactivated by a mask option.
data sheet u12801ej4v0ds00 11 m m m m pd77110, 77111, 77112 pin name bstb : bus strobe clkin : clock input clkout : clock output d0 - d15 : 16-bit data bus da0 - da14 : external data memory address bus ev dd : power supply for i/o pins gnd : ground ha0, ha1 : host data access hcs : host chip select hd0 - hd7 : host data bus holdak : hold acknowledge holdrq : hold request hrd : host read hre : host read enable hwe : host write enable hwr : host write i.c. : internally connected int1 - int4 : interrupt iv dd : power supply for dsp core mrd : memory read output mwr : memory write output nc : non-connection nu : not used p0 - p3 : port pll0 - pll2 : pll multiple rate set reset : reset sck1, sck2 : serial clock input si1, si2 : serial data input siak1 : serial input acknowledge sien1, sien2 : serial input enable so1, so2 : serial data output soen1, soen2 : serial output enable sorq1 : serial output request tck : test clock input tdi : test data input tdo : test data output tice : test in-circuit emulator tms : test mode select trst : test reset wakeup : wakeup from stop mode x/y : x/y memory select
data sheet u12801ej4v0ds00 12 m m m m pd77110, 77111, 77112 contents 1. pin function ................................................................................................................ ................. 13 1.1 pin function description .................................................................................................... ...... 13 1.2 connection of unused pins................................................................................................... ... 18 2. function outline............................................................................................................ ............ 20 2.1 program control unit ........................................................................................................ ........ 20 2.2 arithmetic unit ............................................................................................................. .............. 21 2.3 data memory unit ............................................................................................................ .......... 22 2.4 peripheral units ............................................................................................................ ............. 22 3. clock generator ............................................................................................................. ......... 23 4. reset function .............................................................................................................. ............. 23 4.1 hardware reset.............................................................................................................. ............ 23 4.2 initializing pll ............................................................................................................ ............... 24 5. functions of boot-up rom.................................................................................................. .24 5.1 boot at reset............................................................................................................... ............... 24 5.2 reboot ...................................................................................................................... .................. 25 5.3 signature operation ......................................................................................................... ......... 26 6. standby modes ............................................................................................................... ............ 26 6.1 halt mode................................................................................................................... .............. 26 6.2 stop mode................................................................................................................... .............. 27 7. memory map .................................................................................................................. ................ 27 7.1 instruction memory .......................................................................................................... ......... 27 7.2 data memory ................................................................................................................. ............. 29 8. mask option................................................................................................................. ................. 30 8.1 clock control options....................................................................................................... ........ 30 8.2 wakeup function............................................................................................................. ........ 31 8.3 mask option equivalent function of m m m m pd77110 ..................................................................... 31 9. instructions ................................................................................................................. ................ 33 9.1 outline of instructions ..................................................................................................... ......... 33 9.2 instruction set and operation ............................................................................................... ... 34 10. electrical specifications .................................................................................................. ... 40 11. package ..................................................................................................................... ..................... 72 12. recommended soldering conditions ............................................................................... 75
data sheet u12801ej4v0ds00 13 m m m m pd77110, 77111, 77112 1. pin function because the pin numbers differ depending on the package, refer to the diagram of the package to be used. 1.1 pin function description ? power supply pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: iv dd 35, 77, 85 31, 63, 71 a5, a7, j5 - power to dsp core (+2.5 v) - ev dd 25, 50, 64, 75, 100 10, 20, 40, 50, 60, 80 a1, a9, e1, e9, j1, j9 - power to i/o pins (+3 v) - gnd 1, 26, 36, 51, 65, 76, 78, 86 1, 11, 21, 32, 41, 51, 61, 64, 72 a8, b2, b5, b7, e2, e8, h5, h8, j2 - ground - ? system control pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: clkin 74 62 c7 input system clock input - clkout 73 59 b8 output internal system clock output - reset 87 73 c4 input internal system reset si gnal input pll0 53 -- input p2 pll1 52 -- input p3 pll2 49 -- input pll multiple setting input ( m pd77110 only) ? determines the pll multiple at reset as followings: pll2: pll1: pll0: 000 : selects pll multiple of 1. 001 : selects pll multiple of 2. 010 : selects pll multiple of 3. : 111 : selects pll multiple of 8. ? these pins have no function on the m pd77111 and 77112 . - wakeup 88 74 a4 input stop mode release signal input. ? when this pin is asserted active, the stop mode is released. the function of this pin can be activated or deactivated by a mask option. ? this pin is always valid on the m pd77110 . int4
data sheet u12801ej4v0ds00 14 m m m m pd77110, 77111, 77112 ? interrupt pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: int1 - int3 91 - 89 77 - 75 d4, a3, b4 input - int4 88 74 a4 input external maskable interrupt input. ? detected at the falling edge. wakeup ? external data memory interface pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: x/y 99 -- output (3s) memory select signal output. 0: uses x memory. 1: uses y memory. - da0 - da14 16 - 2 -- output (3s) address bus of external data memory. ? accesses the external memory. ? continuously outputs the external memory address accessed last when the external memory is not being accessed. kept low (0x000) if the external memory is never accessed after reset. ? da14 is nc (no connection) and does not function on the m pd77112. - d0 - d15 34 - 27, 24 - 17 -- i/o (3s) 16-bit data bus. ? accesses the external memory. - mrd 97 -- output (3s) read output ? external memory read - mwr 96 -- output (3s) write output ? external memory write - holdrq 92 -- input hold request signal ? input a low level to this pin when the external device uses the external data memory bus of the m pd77110 and 77112. - bstb 94 -- output bus strobe signal ? this pin goes low when the m pd77110 and 77112 use the external data memory bus. - holdak 93 -- output hold acknowledge signal ? this pin goes low when the external device is enabled to use the external data memory bus of the m pd77110 and 77112. - remark pins marked 3s under the heading i/o go into a high-impedance state in the following conditions: x/y, da0-da14, mrd, mwr: when the bus is released (holdak = low level) d0-d15: when the external data memory is not being accessed and when the bus is released (holdak = low level)
data sheet u12801ej4v0ds00 15 m m m m pd77110, 77111, 77112 ? serial interface pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: sck1 39 24 j3 input serial 1 clock input - sorq1 42 27 j4 output serial output 1 request - soen1 43 28 h4 input serial output 1 enable - so1 41 26 g4 output (3s) serial data output 1 - sien1 38 23 h3 input serial input 1 enable - si1 37 22 g3 input serial data input 1 - siak1 40 25 f4 output serial input 1 acknowledge - sck2 46 33 j6 input serial 2 clock input - soen2 44 29 f5 input serial output 2 enable - so2 45 30 g5 output (3s) serial data output 2 - sien2 47 34 g6 input serial input 2 enable - si2 48 35 h6 input serial data input 2 - remark the pins marked 3s under the heading i/o go into a high-impedance state on completion of data transfer and input of the hardware reset (reset) signal.
data sheet u12801ej4v0ds00 16 m m m m pd77110, 77111, 77112 ? host interface pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: ha1 72 58 b9 input specifies the register to be accessed by hd7 through hd0. ? 1: accesses the host interface status register (hst). ? 0: accesses the host transmit data register (hdt (out)) when read (hrd = 0), and host receive data register (hdt (in)) when written (hwr = 0). - ha0 71 57 c8 input specifies the register to be accessed by hd7 through hd0. ? 1: accesses bits 15 through 8 of hst, hdt (in), and hdt (out). ? 0: accesses bits 7 through 0 of hst, hdt (in), and hdt (out). - hcs 68 54 d7 input chip select input - hrd 69 55 d8 input host read input - hwr 70 56 c9 input host write input - hre 66 52 e6 output host read enable output - hwe 67 53 d9 output host write enable output - hd0 - hd7 63 - 56 49 - 42 e7, f7, f9, f8, g8, g9, g7, h9 i/o (3s) 8-bit host data bus - remark the pins marked 3s under the heading i/o go into a high-impedance state when the host interface is not being accessed. ? i/o ports pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: p0 55 39 j8 i/o - p1 54 38 h7 i/o - p2 53 37 f6 i/o pll0 note p3 52 36 j7 i/o general-purpose i/o port pll1 note note only the m pd77110. the m pd77111 and 77112 have no multiplexed pins.
data sheet u12801ej4v0ds00 17 m m m m pd77110, 77111, 77112 ? debugging interface pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: tdo 79 65 d6 output - tice 80 66 c6 output - tck 81 67 a6 input - tdi 82 68 b6 input - tms 83 69 d5 input - trst 84 70 c5 input for debugging - ? others pin no. pin name 100-pin tqfp 80-pin tqfp 80-pin fbga i/o function shared by: i.c. 98 --- internally connected. leave this pin unconnected. - nu 95 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 16, 17, 18, 19, 78, 79 a2, b1, b3, c1, c2, c3, d1, d2, d3, e3, e4, f1, f2, f3, g1, g2, h1, h2 - no function pins. connect these pins to ev dd . - nc 2, 49 --- no-connect pins (with m pd77112). leave these pins unconnected. - caution if any signal is input to these pins or if an attempt is made to read these pins, the normal operation of the m m m m pd77110, 77111, and 77112 is not guaranteed.
data sheet u12801ej4v0ds00 18 m m m m pd77110, 77111, 77112 1.2 connection of unused pins 1.2.1 connection of function pins when mounting, connect unused pins as follows: pin i/o recommended connection int1 - int4 input connect to ev dd . x/y output da0 - da14 output leave unconnected. d0 - d15 note 1 i/o connect to ev dd via pull-up resistor, or connect to gnd via pull-down resistor. mrd, mwr output leave unconnected. holdrq input connect to ev dd . bstb, holdak output leave unconnected. sck1, sck2 input si1, si2 input connect to ev dd or gnd. sien1, sien2 input soen1, soen2 input connect to gnd. sorq1 output so1, so2 output siak1 output leave unconnected. ha0, ha1 input connect to ev dd or gnd. hcs, hrd, hwr input connect to ev dd . hre, hwe output leave unconnected. hd0 - hd7 note 2 i/o p0 - p3 i/o connect to ev dd via pull-up resistor, or connect to gnd via pull-down resistor. tck input connect to gnd via pull-down resistor. tdo, tice output leave unconnected. tms, tdi input leave unconnected. (internally pulled up). trst input leave unconnected. (internally pulled down). clkout output leave unconnected. notes 1. these pins may be left unconnected if the external data memory is not accessed in the program. however, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered. 2. these pins may be left unconnected if hcs, hrd, and hwr are fixed to the high level. however, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered.
data sheet u12801ej4v0ds00 19 m m m m pd77110, 77111, 77112 1.2.2 connection of no-function pins pin i/o recommended connection i.c. - leave unconnected. nu - connect to ev dd . nc - leave unconnected.
data sheet u12801ej4v0ds00 20 m m m m pd77110, 77111, 77112 2. function outline 2.1 program control unit this unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode of the dsp. 2.1.1 cpu control a three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as branch instructions, are executed in one system clock. 2.1.2 interrupt control interrupt requests input from external pins (int1 through int4) or generated by the internal peripherals (serial interface and host interface) are serviced. the interrupt of each interrupt source can be enabled or disabled. multiple interrupts are also supported. 2.1.3 loop control task a loop function without any hardware overhead is provided. a loop stack with four levels is provided to support multiple loops. 2.1.4 pc stack a 15-level pc stack that stores the program counter supports multiple interrupts and subroutine calls. 2.1.5 pll a pll is provided as a clock generator that can multiply or divide an external clock input to supply an operating clock to the dsp. the multiplication and division ratio are set as follows: ? m pd77110: a multiple of 1 to 8 is specified by an external pin (division ratio is fixed). ? m pd77111 and 77112: a multiple of 1 to 16 or a division ratio of 1/1 to 1/16 can be set by a mask option. two standby modes are available for lowering the power consumption while the dsp is not in use. ? halt mode : set by execution of the halt instruction. the current consumption drops to several ma. the normal operation mode is recovered by an interrupt or hardware reset. ? stop mode: set by execution of the stop instruction. the current consumption drops to several 10 m a. the normal operation mode is recovered by hardware reset or wakeup pin note . note if the wakeup function is activated by mask option 2.1.6 instruction memory the capacity and type of the memory differ depending on the model of the dsp. 64 words of the instruction ram are allocated to interrupt vectors. a boot-up rom that boots up the instruction ram is provided, and the instruction ram can be initialized or rewritten by self boot (boot from the internal data rom or external data space) or host boot (boot via host interface). ? m pd77110: 35.5k-word ram ? m pd77111, 77112: 1k-word ram and 31.75k-word rom
data sheet u12801ej4v0ds00 21 m m m m pd77110, 77111, 77112 2.2 arithmetic unit this unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data alu, 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 general-purpose registers (r0 through r7) these eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to data memory. a general-purpose register (r0 to r7) is made up of three parts: r0l through r7l (bits 15 through 0), r0h through r7h (bits 31 through 16), and r0e through r7e (bits 39 through 32). depending on the type of operation, rnl, rnh, and rne are used as one register or in different combinations. 2.2.2 multiply accumulator (mac) the mac multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and outputs a 40-bit value. the mac is provided with a shifter (msft: mac shifter) at the stage preceding the input stage. this shifter can arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right . 2.2.3 arithmetic logic unit (alu) this unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value. 2.2.4 barrel shifter (bsft: barrel shifter) the barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value. the data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or logically shifted to the right, in which case 0 is inserted from the msb.
data sheet u12801ej4v0ds00 22 m m m m pd77110, 77111, 77112 2.3 data memory unit the data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 data memory the capacity and type of the memory differ depending on the model of the dsp. all dsps have two banks of data memory (x data memory and y data memory). a 64-word peripheral area is assigned in the data memory space. ? m pd77110: ram of 24k words 2 banks ? m pd77111, 77112: ram of 3k words 2 banks and rom of 16k words 2 banks in addition, some models have an external data memory interface so that the external memory can be expanded. ? m pd77110: external data memory of 32k words 2 banks ? m pd77112: external data memory of 16k words 2 banks 2.3.2 data addressing unit an independent data addressing unit is provided for each of the x data memory and y data memory spaces. each data addressing unit has four data pointers (dpn), four index registers (dnn), one modulo register (dmx or dmy), and an address alu. 2.4 peripheral units a serial interface, host interface, general-purpose i/o port, and wait cycle register are provided. all these internal peripherals are mapped to the x data memory and y data memory spaces, and are accessed from program as memory-mapped i/os. 2.4.1 serial interface (sio) two serial interfaces are provided. these serial interfaces have the following features: ? serial clock : supplied from external source to each interface. the same clock is used for input and output on the interface. ? frame length: 8 or 16 bits, and msb or lsb first selectable for each interface and input or output ? handshake : handshaking with external devices is implemented with a dedicated status signal. with the internal units, polling, wait, or interrupt are used. 2.4.2 host interface (hio) this is an 8-bit parallel port that inputs data from or outputs data to an external host cpu or dma controller. in the dsp, a 16-bit register is mapped to memory for input data, output data, and status. handshaking with an external device is implemented by using a dedicated status signal. handshaking with internal units is achieved by means of polling, wait, or interrupts. 2.4.3 general-purpose i/o port (pio) this is a 4-bit i/o port that can be set in the input or output mode in 1-bit units.
data sheet u12801ej4v0ds00 23 m m m m pd77110, 77111, 77112 2.4.4 wait cycle register the number of wait cycles to be inserted when the external data memory area is accessed can be specified in advance by using a register (dwtr) note . the number of wait cycles that can be set is 1, 3, or 7. note this function is not available on the m pd77111 because this dsp does not have an external data area. 3. clock generator the clock generator generates an internal system clock based on the external clock input from the clkin pin and supplies the generated clock to the internal units of the dsp. for details of how to set the pll multiple, refer to 4.2 initializing pll , 8.1 clock control options , and 8.3.1 settings related to clock control . stop mode pll control circuit output divider halt divider halt mode internal system clock m clkout clkin n l 4. reset function when a low level of a specified width is input to the reset pin, the device is initialized. 4.1 hardware reset if the reset pin is asserted active (low level) for a specified period, the internal circuitry of the dsp is initialized. if the reset pin is then deasserted inactive (high level), boot processing of the instruction ram is performed according to the status of the port pins (p0 and p1). after boot processing, processing is executed starting from the instruction at address 0x200 of instruction memory (reset entry). on power application, the reset pin must be asserted active (low level) after 4 input clocks have been input with the reset pin in the inactive status (high level), after the supply voltage has reached the level of the operating voltage. in other words, no power-on reset function is available. on power application, the pll must be initialized.
data sheet u12801ej4v0ds00 24 m m m m pd77110, 77111, 77112 4.2 initializing pll initializing the pll starts from the 1024th input clock after the reset pin has been asserted active (low level). initialization takes 1024 clocks and it takes the pll 100 m s to be locked. after that, the dsp operates with the set value of the pll specified by a mask option ( m pd77111 or 77112) or an external pin ( m pd77110) when the reset pin is deasserted inactive (high level). after initializing the pll, be sure to execute boot-up processing to re-initialize the internal ram. to initialize the pll, the internal memory contents and register status of the dsp are not retained. if the reset pin is deasserted inactive before the pll initialization mode is set, the dsp is normally reset (the pll is not initialized). clkin reset pll initialization mode 1024 1 2048 pll lock time approx. 100 s pll initialization (internal status) m caution do not deassert the reset signal inactive in the pll initialization mode and during pll lock period. 5. functions of boot-up rom to rewrite the contents of the instruction memory on power application or from program, boot up the instruction ram by using the internal boot-up rom. the m pd77110 has a function to verify the contents of the internal instruction ram in the boot-up rom. 5.1 boot at reset after hardware reset has been cleared, the boot program first reads the general-purpose i/o ports p0 and p1 and, depending on their bit pattern, determines the boot mode (self boot or host boot). after boot processing, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. the pins (p0 and p1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the duration of 12 clocks after reset has been cleared (the clock is input from clkin). p1 p0 boot mode 00 does not execute boot but branches to address 0x200 note . 0 1 executes host boot and then branches to address 0x200. 1 1 executes self boot and then branches to address 0x200. 1 0 setting prohibited note this setting is used when the dsp must be reset to recover from the standby mode after reset boot has been executed once.
data sheet u12801ej4v0ds00 25 m m m m pd77110, 77111, 77112 5.1.1 self boot the boot-up rom transfers the instruction code stored in the data memory space to the instruction ram, based on the boot parameter written to address 0x4000 of the y data memory. generally, with a mask rom model ( m pd77111 or 77112), this function is implemented by storing the instructions to be booted in the data rom. in addition, the instructions to be booted can be also stored in an external data area in the form of flash rom, and self boot can be executed from this external data area. with the m pd77110, the value of address 0x4000 of the y data memory is undefined on power application, because this address is in ram. therefore, with the m pd77110, the self boot mode cannot be selected on power application, and host boot must be executed. this also applies when the pll is initialized. by writing a boot parameter to address 0x4000 or those that follow of the y data memory, self boot can be executed when the reset signal is subsequently input (except the reset that initializes the pll). in this case, however, the instructions to be booted are only those at address 0x0200 through 0x0fff of the instruction ram. 5.1.2 host boot in this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the instruction ram. with the m pd77110, the host boot mode is used on power application. the boot instruction area is the instruction ram from addresses 0x0200 through 0x0fff. to boot up the instruction ram from 0x4000 through 0xbfff, host reboot is used. 5.2 reboot by calling the next reboot entry from the program, the contents of the instruction ram can be rewritten. in particular, the m pd77110 has a reboot function that boots up the instruction ram from 0x4000 through 0xbfff. reboot mode entry address word reboot 0x2 x memory byte reboot 0x4 word reboot 0x1 self boot y memory byte reboot 0x3 host boot host reboot 0x6 ( m pd77110) 0x5 ( m pd77111, 77112) 5.2.1 self reboot the instruction codes stored in the data memory are transferred to the instruction ram. this boot mode cannot be used with the m pd77110. set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot. ? r7l : number of instruction steps for rebooting ? dp3: first address of x memory in which instruction codes are stored (in the case of reboot from x memory), or first address of the instruction memory to be loaded (in the case of reboot from y memory) ? dp7: first address of instruction memory to be loaded (in the case of reboot from x memory), or first address of x memory in which instruction codes are stored (in the case of reboot from y memory)
data sheet u12801ej4v0ds00 26 m m m m pd77110, 77111, 77112 5.2.2 host reboot an instruction code is obtained via the host interface and transferred to the instruction ram. with the m pd77110, the host reboot mode is used to boot up the instruction ram from addresses 0x4000 through 0xbfff. areas 0x0200 through 0x0fff and 0x4000 through 0xbfff cannot be rebooted all at once. the entry address of the m pd77110 is 0x6, and that of the m pd77111 and 77112 is 0x5. host reboot is executed by calling this address after setting the following parameter: ? r7l : number of instruction steps for rebooting ? dp3: first address of instruction memory to be loaded 5.3 signature operation the m pd77110 has a signature operation function so that the contents of the internal instruction ram can be verified. the signature operation performs a specific arithmetic operation on the data in the instruction ram booted up, and returns the result to a register. perform the signature operation in advance on the device when it is operating normally, and repeat the signature operation later to check whether the data in ram is correct by comparing the operation result with the previous result. if the results are identical, there is no problem. the entry address is 0x9. execute the operation by calling this address after setting the following parameter. note that the operation cannot be performed on the areas 0x0200 through 0x0fff and 0x4000 through 0xbfff at the same time. the operation result is stored in register r7. ? r7l: number of instruction steps for operation ? dp3: first address of instruction memory for operation 6. standby modes two standby modes are available. by executing the corresponding instruction, each mode is set and the power consumption can be reduced. 6.1 halt mode to set this mode, execute the halt instruction. in this mode, functions other than clock circuit and pll are stopped to reduce the current consumption. to release the halt mode, use an interrupt or hardware reset. when releasing the halt mode using an interrupt, the contents of the internal registers and memory are retained. it takes several 10 system clocks to release the halt mode when the halt mode is released using an interrupt. in the halt mode, the clock circuit of the m pd77111 family supplies the following clock as the internal system clock. the clock output from the clkout pin is as follows. the clock output from the clkout pin, however, has a high-level width that is equivalent to 1 cycle of the normal operation (i.e., the duty factor is not 50%). ? m pd77110: 1/8 of internal system clock ? m pd77111, 77112: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)
data sheet u12801ej4v0ds00 27 m m m m pd77110, 77111, 77112 6.2 stop mode to set this mode, execute the stop instruction. in this mode, all the functions, including the clock circuit and pll, are stopped and the power consumption is minimized with only leakage current flowing. to release the stop mode, use hardware reset or wakeup pin. when releasing the stop mode by using the wakeup pin, the contents of the internal registers and memory are retained, but it takes several 100 m s to release the mode. the wakeup pin is multiplexed with the int4 pin. usually, this pin functions as an interrupt pin, but functions as the wakeup pin when it is asserted active in the stop mode. whether the wakeup pin is used to release the stop mode is selected by mask option. for details, refer to 8.2 wakeup function and 8.3.2 wakeup function . 7. memory map a harvard architecture, in which the instruction memory space and data memory space are separated is employed. 7.1 instruction memory 7.1.1 instruction memory map the instruction memory space consists of 64k words 32 bits, and the capacity and type of the memory differ depending on the product. system pd77110 mm pd77111, 77112 internal instruction ram (32k words) system system internal instruction rom (31.75k words) system internal instruction ram (1k words) vector area (64 words) system boot-up rom (256 words) internal instruction ram (3.5k words) vector area (64 words) system boot-up rom (256 words) 0xffff 0xc000 0xbfff 0xbf00 0xbeff 0x0600 0x05ff 0x4000 0x3fff 0x1000 0x0fff 0x0240 0x023f 0x0200 0x01ff 0x0100 0x00ff 0x0000 caution programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. if these addresses are accessed, the normal operation of the device cannot be guaranteed.
data sheet u12801ej4v0ds00 28 m m m m pd77110, 77111, 77112 7.1.2 interrupt vector table addresses 0x200 through 0x23f of the instruction memory are entry points (vectors) of interrupts. four instruction addresses are assigned to each interrupt source. vector interrupt source 0x200 reset 0x204 0x208 0x20c reserved 0x210 int1 0x214 int2 0x218 int3 0x21c int4 0x220 si1 input 0x224 so1 output 0x228 si2 input 0x22c so2 output 0x230 hi input 0x234 ho output 0x238 0x23c reserved cautions 1. although reset is not an interrupt, it is handled like an interrupt as an entry to a vector. 2. it is recommended that unused interrupt source vectors be used to branch an error processing routine. 3. because a vector area also exists in the internal ram area of the mask rom model, this area must be booted up. in addition, because the entry address after reset is 0x200, address 0x200 must be booted up even when the internal instruction ram and interrupts are not used.
data sheet u12801ej4v0ds00 29 m m m m pd77110, 77111, 77112 7.2 data memory 7.2.1 data memory map the data memory space consists of an x memory space and a y memory space of 64k words 16 bits each, and the memory capacity and memory type differ depending on the product. external data memory (32k words) data ram (16k words) system peripheral (64 words) system data ram (4k words) system data ram (4k words) system data rom (16k words) system peripheral (64 words) peripheral (64 words) system data ram (3k words) system data rom (16k words) external data memory (16k words) system pd77110 mmm pd77111 pd77112 system data ram (3k words) 0xffff 0x4000 0x3fff 0x3840 0x383f 0x3800 0x37ff 0x3000 0x2fff 0x2000 0x1fff 0x1000 0x0fff 0x0000 0x8000 0x7fff 0x0c00 0x0bff 0xc000 0xbfff caution programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. if these addresses are accessed, the normal operation of the device cannot be guaranteed.
data sheet u12801ej4v0ds00 30 m m m m pd77110, 77111, 77112 7.2.2 internal peripherals the internal peripherals are mapped to the internal data memory space. x/y memory address register name function peripheral name 0x3800 sdt1 first serial data register 0x3801 sst1 first serial status register 0x3802 sdt2 second serial data register 0x3803 sst2 second serial status register sio 0x3804 pdt port data register 0x3805 pcd port command register iop 0x3806 hdt host data register 0x3807 hst host status register hio 0x3808 dwtr data memory wait cycle register wtr 0x3809 - 0x383f reserved area caution do not access this area. - cautions 1. the register names listed in this table are not reserved words of the assembler or the c language. therefore, when using these names in assembler or c, the user must define them. 2. the same register is accessed, as long as the address is the same, regardless of whether the x memory space or y memory space is accessed. 3. even different registers cannot be accessed at the same time from both the x and y memory spaces. 8. mask option the m pd77111 and 77112 have mask options that must be specified when an order for a rom is placed. this section explains these mask options. the mask options are specified in the workbench (wb77016) development tool. to order a mask rom, output a mask rom ordering file format (.msk file) using wb77016. 8.1 clock control options the following four clock related options must be specified. ? pll multiple ? output division ratio ? halt division ratio ? validity of clkout pin
data sheet u12801ej4v0ds00 31 m m m m pd77110, 77111, 77112 when the pll multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each operation mode and operating clock is as follows: operation mode clock supplied inside dsp normal operation mode m/n times external input clock halt mode m/n/l times external input clock stop mode stopped the pll control circuit multiplies the input clock by an integer from 1 to 16. specify the mask option of the pll multiple so that the multiplied frequency falls within the specified pll lock frequency range. the output divider divides the clock multiplied by the pll by an integer from 1 to 16. specify the mask option of the output division ratio so that the frequency m/n times the external input clock supplied to the dsp falls within the specified operating frequency range of the dsp. the halt divider functions only in the halt mode. it divides the clock of the output divider by an integer from 1 to 16 and supplies the divided clock to the internal circuitry. specify the mask option of the halt division ratio so that necessary division can be performed. whether the clock supplied to the internal circuitry of the dsp (internal system clock) is output or not output from the clkout pin can be specified. specify the mask option as necessary. if an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from the clkout pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%). 8.2 wakeup function the wakeup pin can be used to release the stop mode as well as a hardware reset. if the stop mode is released by means of a hardware reset, the status before the stop mode was set cannot be restored after the stop mode has been released. if the wakeup pin is used, however, the status before the stop mode is set can be retained and program execution can be resumed starting from the instruction after the stop instruction. whether the wakeup pin is used to release the stop mode can be specified by a mask option. when the wakeup function is specified valid, the wakeup pin is multiplexed with the int4 pin and it usually functions as an interrupt pin. the pin functions as the wakeup pin only in the stop mode (if this pin is asserted active in the stop mode, it is used only to release the stop mode, and execution does not branch to an interrupt vector). 8.3 mask option equivalent function of m m m m pd77110 because the m pd77110 does not have mask options, the multiple of the pll cannot be specified in the same manner as the m pd77111 and 77112. however, an external pin on the m pd77110 has a function equivalent to the mask option. care must be exercised when using the m pd77110, including when it is used to emulate the m pd77111 and 77112.
data sheet u12801ej4v0ds00 32 m m m m pd77110, 77111, 77112 8.3.1 settings related to clock control external pins pll0 through pll2 are used to set the multiple of the pll. pll0 and pll1 are multiplexed with general-purpose i/o ports p2 and p3, and can be used as pll setting pins only when it is so specified. the multiple must be an integer from 1 to 8. 000 m = 1 001 m = 2 : 111 m = 8 the output division ratio is fixed to 1/1 and the halt division ratio is fixed to 1/8. where the pll multiple is m, the relationship between each operation mode and operating clock is as follows: operation mode clock supplied to dsp normal operation mode m times external input clock halt mode m/8 times external input clock stop mode stopped for details on how to set the pll multiple, refer to 4.2 initializing pll . because the setting of pll0 through pll2 becomes valid in the pll initialization mode, the value of pll0 through pll2 must be fixed before the pll initialization mode is set. the option that makes clkout pin output valid or invalid is fixed to valid. 8.3.2 wakeup function the wakeup function of the m pd77110 is fixed to valid.
data sheet u12801ej4v0ds00 33 m m m m pd77110, 77111, 77112 9. instructions 9.1 outline of instructions an instruction consists of 32 bits. almost all the instructions, except some such as branch instructions, are executed with one system clock. the maximum instruction cycle of the m pd77110 is 15.3 ns. the maximum instruction cycle of the m pd77111 and 77112 is 13.3 ns. the following nine types of instructions are available: (1) trinomial operation instructions these instructions specify an operation by the mac. as the operands, three general-purpose registers can be specified. (2) binomial operation instructions these instructions specify an operation by the mac, alu, or bsft. as the operands, two general-purpose registers can be specified. an immediate value can be specified for some of these instructions, instead of a general-purpose register, for one input. (3) uninominal operation instructions these instructions specify an operation by the alu. as the operands, one general-purpose register can be specified. (4) load/store instructions these instructions transfer 16-bit values between memory and a general-purpose register. any general-purpose register can be specified as the transfer source or destination. (5) register-to-register transfer instructions these instructions transfer data from one general-purpose register to another. (6) immediate value setting instructions these instructions write an immediate value to a general-purpose register and the registers of the address operation unit. (7) branch instructions these instruction specify branching of program execution. (8) hardware loop instructions these instruction specify repetitive execution of an instruction. (9) control instructions these instructions are used to control the program.
data sheet u12801ej4v0ds00 34 m m m m pd77110, 77111, 77112 9.2 instruction set and operation an operation is written in the operation field for each instruction in accordance with the operation representation format of that instruction. if two or more parameters can be written, select one of them. (a) representation formats and selectable registers the following table shows the representation formats and selectable registers. representation format selectable register r0, r0 , r0 2 r0 - r7 ri, ri r0l - r7l rh, rh r0h - r7h re r0e - r7e reh r0eh - r7eh dp dp0 - dp7 dn dn0 - dn7 dm dmx, dmy dpx dp0 - dp3 dpy dp4 - dp7 dpx_mod dpn, dpn++, dpn -- , dpn##, dpn%%, !dpn## (n = 0 - 3) dpy_mod dpn, dpn++, dpn -- , dpn##, dpn%%, !dpn## (n = 4 - 7) dp_imm dpn##imm (n = 0 - 7) *xxx contents of memory with address xxx if the contents of the dp0 register are 1000, *dp0 indicates the contents of address 1000 of the memory.
data sheet u12801ej4v0ds00 35 m m m m pd77110, 77111, 77112 (b) modifying data pointer the data pointer is modified after the memory has been accessed. the result of modification becomes valid starting from the instruction that immediately follows. the data pointer cannot be modified. example operation dpn nothing is done (value of dpn is not changed.) dpn++ dpn ? dpn + 1 dpn -- dpn ? dpn - 1 dpn## dpn ? dpn + dnn (adds value of corresponding dn0 to dn7 to dp0 to dp7.) example: dp0 ? dp0 + dn0 (n = 0 - 3) dpn = ((dp l + dnn) mod (dmx + 1)) + dp h dpn%% (n = 4 - 7) dpn = ((dp l + dnn) mod (dmy + 1)) + dp h !dpn## reverses bits of dpn and then accesses memory. after memory access, dpn ? dpn + dnn dpn##imm dpn ? dpn + imm (c) instructions that can be simultaneously written instructions that can be simultaneously written are indicated by o. (d) status of overflow flag (ov) the status of the overflow flag is indicated by the following symbol: z : not affected : set to 1 when overflow occurs caution if an overflow does not occur as a result of an operation, the overflow flag is not reset but retains the status before the operation.
data sheet u12801ej4v0ds00 36 m m m m pd77110, 77111, 77112 instruction set instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate- value bran- ch loop cont- rol ov multiply add ro = ro + rh * rh ro ? ro + rh * rh { multiply sub ro = ro - rh * rh ro ? ro - rh * rh { sign unsign multiply add ro = ro + rh * rl (rl is in positive integer format.) ro ? ro + rh * rl { unsign unsign multiply add ro = ro + rl * rl (rl and rl are in positive integer format.) ro ? ro + rl * rl { 1-bit shift multiply add ro = (ro>>1) + rh * rh ro ? ro 2 + rh * rh { trinomial operation 16-bit shift multiply add ro = (ro>>16) + rh * rh ro ? ro 2 16 + rh * rh {z multiply ro = rh * rh ro ? rh * rh {z add ro 2 = ro + ro ro 2 ? ro + ro { immediate add ro = ro + imm ro ? ro + imm (where imm 1 1) sub ro 2 = ro - ro ro 2 ? ro - ro { immediate sub ro = ro - imm ro ? ro - imm (where imm 1 1) arithmetic right shift ro = ro sra rl ro ? ro >> rl {z immediate arithmetic right shift ro = ro sra imm ro ? ro >> imm z logical right shift ro = ro srl rl ro ? ro >> rl {z immediate logical right shift ro = ro srl imm ro ? ro >> imm z logical left shift ro = ro sll rl ro ? ro << rl {z immediate logical left shift ro = ro sll imm ro ? ro << imm z and ro 2 = ro & ro ro 2 ? ro & ro {z immediate and ro = ro & imm ro ? ro & imm z or ro 2 = ro ? ro ro 2 ? ro ? ro {z immediate or ro = ro ? imm ro ? ro ? imm z exclusive or ro 2 = ro ro ro 2 ? ro ro {z binomial operation immediate exclusive or ro = ro imm ro ? ro imm z
data sheet u12801ej4v0ds00 37 m m m m pd77110, 77111, 77112 instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate- value bran- ch loop cont- rol ov binomial operation less than ro 2 = lt (ro, ro ) if (ro < ro ) {ro 2 ? 0x0000000001} else {ro 2 ? 0x0000000000} {z clear clr (ro) ro ? 0x0000000000 {{z increment ro = ro + 1 ro ? ro + 1 {{ decrement ro = ro - 1ro ? ro - 1 {{ absolute value ro = abs (ro) if (ro < 0) {ro ? - ro} else {ro ? ro} {{ 1s complement ro = ~ ro ro ? ~ ro {{z 2s complement ro = - ro ro ? - ro {{ clip ro = clip (ro) if ( ro > 0x007fffffff) {ro ? 0x007fffffff} elseif {ro < 0xff80000000} {ro ? 0xff80000000} else {ro ? ro} {{z round ro = round (ro) if (ro > 0x007fff0000) {ro ? 0x007fff0000} elseif {ro < 0xff80000000} {ro ? 0xff80000000} else {ro ? (ro + 0x8000) & 0xffffff0000} {{z exponent ro = exp (ro) ro ? log 2 ( 1 ro ) {{z substitution ro = ro ro ? ro {{z accumulated addition ro + = ro ro ? ro + ro {{ accumulated subtraction ro - = ro ro ? ro - ro {{ uninom- inal operation division ro / = ro if (sign (ro ) == sign (ro)) {ro ? (ro - ro) << 1} else {ro ? (ro + ro)<<1} if (sign (ro )==0) {ro ? ro + 1} {{
data sheet u12801ej4v0ds00 38 m m m m pd77110, 77111, 77112 instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate- value bran- ch loop cont- rol ov ro = *dpx_mod ro = *dpy_mod ro ? *dpx, ro ? *dpy ro = *dpx_mod *dpy_mod = rh ro ? *dpx, *dpy ? rh *dpx_mod = rh ro = *dpy_mod *dpx ? rh, ro ? *dpy parallel load/store notes 1, 2 *dpx_mod = rh *dpy_mod = rh *dpx ? rh, *dpy ? rh {{{ z dest = *dpx_mod dest = *dpy_mod dest ? *dpx, dest ? *dpy dest = *dpx_mod *dpy_mod = source dest ? *dpx, *dpy ? source *dpx_mod = source dest = *dpy_mod *dpx ? source, dest ? *dpy partial load/ store notes 1, 2, 3 *dpx_mod = source *dpy_mod = source *dpx ? source, *dpy ? source z dest = *addr dest ? *addr direct addressing load/store note 4 *addr = source *addr ? source z dest = *dp_imm dest ? *dp load/ store immediate value index load/store note 5 *dp_imm = source *dp ? source z dest = rl dest ? rl register- to-register transfer register-to- register transfer note 6 rl = source rl ? source {z rl = imm (where imm = 0 to 0xffff) rl ? imm dp = imm (where imm = 0 to 0xffff) dp ? imm dn = imm (where imm = 0 to 0xffff) dn ? imm immediate value setting immediate value setting dm = imm (where imm = 1 to 0xffff) dm ? imm z notes 1. of the two mnemonics, either one of them or both can be written. 2. after transfer, modification specified by mod is performed. 3. select any of dest, dest = {ro, reh, re, rh, rl}, source, source = {re, rh, rl}. 4. select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, 0: x-0xfff 0: y-0xffff : x (x memory) : y (y memory) addr = . 5. select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 6. select any register other than general-purpose registers as dest and source.
data sheet u12801ej4v0ds00 39 m m m m pd77110, 77111, 77112 instructions simultaneously written flag instruc- tion instruction name mnemonic operation trino- mial bino- mial unino- minal load/ store trans- fer imme- diate- value bran- ch loop cont- rol ov jump jmp imm pc ? imm {z register indirect jump jmp dp pc ? dp {z subroutine call call imm sp ? sp + 1 stk ? pc + 1 pc ? imm {z register indirect subroutine call call dp sp ? sp + 1 stk ? pc + 1 pc ? dp {z return ret pc ? stk sp ? sp - 1 {z branch interrupt return reti pc ? stk stk ? sp - 1 recovery of interrupt enable flag {z repeat rep count start rc ? count rf ? 0 during repeat pc ? pc rc ? rc - 1 end pc ? pc + 1 rf ? 1 z loop loop count (instruction of two or more lines) start rc ? count rf ? 0 during repeat pc ? pc rc ? rc - 1 end pc ? pc + 1 rf ? 1 z hard- ware loop loop hop lpop lc ? lsr3 le ? lsr2 ls ? lsr1 lsp ? lsp - 1 z no operation nop pc ? pc + 1 z halt halt cpu stops. z stop stop cpu, pll, and osc stop. z condition if (ro cond) condition test {{{ z control forget interrupt fint discard interrupt request z
data sheet u12801ej4v0ds00 40 m m m m pd77110, 77111, 77112 10. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol condition rating unit iv dd for dsp core - 0.5 to +3.6 v supply voltage ev dd for i/o pins - 0.5 to +4.6 v input voltage v i - 0.5 to +4.1 v output voltage v o v i < ev dd + 0.5 v - 0.5 to +4.1 v storage temperature t stg - 65 to +150 c operating temperature t a - 40 to +85 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. recommended operating conditions m pd77110 parameter symbol condition min. typ. max. unit iv dd for dsp core 2.3 2.7 v operating voltage ev dd for i/o pins 2.7 3.6 v input voltage v i 0ev dd v m pd77111, 77112 parameter symbol condition min. typ. max. unit iv dd for dsp core 1.8 2.7 v iv dd = 1.8 to 2.7 v 3.3 operating voltage ev dd for i/o pins iv dd = 2.3 to 2.7 v 2.7 3.6 v input voltage v i 0ev dd v capacitance (t a = +25 c, iv dd = 0 v, ev dd = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i 10 pf output capacitance c o 10 pf i/o capacitance c io f = 1 mhz, pins other than those tested: 0 v 10 pf
data sheet u12801ej4v0ds00 41 m m m m pd77110, 77111, 77112 dc characteristics (t a = - - - - 40 to +85 c, with iv dd and ev dd within recommended operating condition range) parameter symbol condition min. typ. max. unit v ihn pins other than below 0.7 ev dd ev dd v high-level input voltage v ihs clkin, reset, int1 - int4, sck1, sien1, soen1, sck2, sien2, soen2 0.8 ev dd ev dd v low-level input voltage v il 0 0.2 ev dd v l oh = - 2.0 ma 0.7 ev dd v high-level output voltage v oh i oh = - 100 m a 0.8 ev dd v low-level output voltage v ol i ol = 2.0 ma 0.2 ev dd v high-level input leakage current i lh other than tdi, tms, and trst v i = ev dd 010 m a low-level input leakage current i ll other than tdi, tms, and trst v i = 0 v - 10 0 m a pull-up pin current i pui tdi, tms, 0 v v i ev dd - 250 0 m a pull-down pin current i pdi trst, 0 v v i ev dd 0 250 m a i dd note 1 during operating, 30 ns, iv dd = 2.7 v tbd 75 ma i ddh in halt mode, t cc = 30 ns, divided by eight, iv dd = 2.7 v tbd 10 ma internal supply current [v ihn = v ihs = ev dd , v il = 0 v, no load] i dds in stop mode, 0 c < t a < 60 c 100 note 2 m a notes 1. the typ. values are when an ordinary program is executed. the max. values are when a special program that brings about frequent switching inside the device is executed. 2. values of m pd77111 and 77112. the parameters of the m pd77110 are still under evaluation. common test criteria of switching characteristics 0.8 ev dd 0.5 ev dd 0.2 ev dd 0.8 ev dd 0.5 ev dd 0.2 ev dd test points clkin, reset, int1 - int4, sck1, sien1, soen1, sck2, sien2, soen2 0.7 ev dd 0.5 ev dd 0.2 ev dd 0.7 ev dd 0.5 ev dd 0.2 ev dd test points input (other than above) 0.5 ev dd 0.5 ev dd test points output
data sheet u12801ej4v0ds00 42 m m m m pd77110, 77111, 77112 m pd77110 (1) m m m m pd77110 ac characteristics (unless otherwise specified, t a = - - - - 40 to +85 c, with iv dd and ev dd within recommended operating condition range) clock timing requirements parameter symbol condition min. typ. max. unit 25 ns clkin cycle time note 1 t ccx pll lock range note 2 10 m 50 mns clkin high-level width t wcxh 12.5 ns clkin low-level width t wcxl 12.5 ns clkin rise/fall time t rfcx 5ns internal clock cycle time requirements note 3 t cc (r) 15.3 ns notes 1. m: multiple 2. this is the range in which the pll is locked (stably oscillates). input t ccx within this range. 3. input t ccx so that the value of (t ccx ? m) satisfies this condition. timing requirements (t a = - - - - 40 to +60 c, iv dd = 2.5 to 2.7 v, ev dd = 2.7 to 3.6 v) parameter symbol condition min. typ. max. unit 25 ns clkin cycle time note 1 t ccx pll lock range note 2 10 m 50 mns clkin high-level width t wcxh 12.5 ns clkin low-level width t wcxl 12.5 ns clkin rise/fall time t rfcx 5ns internal clock cycle time requirements note 2 t cc (r) 13.3 ns notes 1. m: multiple 2. this is the range in which the pll is locked (stably oscillates). input t ccx within this range. 3. input t ccx so that the value of (t ccx ? m) satisfies this condition.
data sheet u12801ej4v0ds00 43 m m m m pd77110, 77111, 77112 m pd77110 switching characteristics parameter symbol condition min. typ. max. unit during normal operation t ccx ? mns internal clock cycle note t cc in halt mode t ccx ? m lns clkout cycle time t cco t cc ns during normal operation t ccx ? 2 - 3ns clkout width t wco in halt mode t ccx ? m - 3ns clkout rise/fall time t rfco 5ns clkout delay time t dco 15 ns note m: multiple, l: halt division ratio clock i/o timing internal clock clkin clkout t ccx t cc, t cc (r) t wcxh t wcxl t rfcx t rfcx t cco t dco t wco t wco t rfco t rfco
data sheet u12801ej4v0ds00 44 m m m m pd77110, 77111, 77112 m pd77110 reset, interrupt timing requirements parameter symbol condition min. typ. max. unit on power application note 1 , in stop mode 100 + 2048t ccx m s reset low-level width t w (rl) during normal operation, in halt mode 4t cc note 2 note 3 ns on power application note 4 4t ccx ns reset recovery time t rec (r) 4t cc note 2 ns wakeup low-level width t w (wakeupl) 100 m s int1 - int4 low-level width t w (intl) 3t cc note 2 ns int1 - int4 recovery time t rec (int) 3t cc ns notes 1. the value on power application is the time from when the supply voltages have reached iv dd = 1.8 v and ev dd = 2.7 v. a stable clock input is also required. 2. note that t cc is eight times this value during normal operation in the halt mode. 3. if the low-level width of reset is greater than 1024t cc , the pll initialization mode is triggered. if there is no need to use the pll initialization mode, set the width to less than 1024t cc . 4. when the power is turned on, a recovery period of 4t ccx is necessary before inputting reset. reset timing reset t w(rl) t rec(r) wakeup timing wakeup t w (wakeupl) interrupt timing int1 - int4 t w (intl) t rec (int)
data sheet u12801ej4v0ds00 45 m m m m pd77110, 77111, 77112 m pd77110 external data memory access timing requirements parameter symbol condition min. typ. max. unit read data setup time t suddrd 18 ns read data hold time t hddrd 0ns switching characteristics parameter symbol condition min. typ. max. unit address cycle time t rcda t cc + (t cc t cdw ) note ns address output hold time t hda 0ns mrd output delay time t ddr 5ns write data output valid time t vddwd 5ns write data output hold time t hddwd 0ns mwr output delay time t ddw 0 0.5 t cc ns mwr output hold time t hda 0ns mwr low-level width t wdwl t cc t cdw - 3 ns mwr high-level width t wdwh 0.5 t cc - 3ns note t cdw : number of data wait cycles
data sheet u12801ej4v0ds00 46 m m m m pd77110, 77111, 77112 m pd77110 external data memory access timing (read) da0 - da14 mrd x/y d0 - d15 t rcda t ddr t ddr t suddrd t hddrd external data memory access timing (write) da0 - da14 x/y mwr d0 - d15 t rcda t ddw t vddwd hi-z hi-z t vddwd t hddwd t wdwl t wdwh t hda t ddw
data sheet u12801ej4v0ds00 47 m m m m pd77110, 77111, 77112 m pd77110 bus arbitration timing requirements parameter symbol condition min. typ. max. unit holdrq setup time t suhrq 0ns holdrq hold time t hhrq 0ns switching characteristics parameter symbol condition min. typ. max. unit bstb hold time t hbs 0ns bstb output delay time t dbs 20 ns holdak output delay time t dhak 18 ns data hold time during bus arbitration t h (bs-d) 25 ns data valid time during bus arbitration t v (bs-d) 25 ns
data sheet u12801ej4v0ds00 48 m m m m pd77110, 77111, 77112 m pd77110 bus arbitration timing (when bus is idle) clkin t suhrq bstb holdrq holdak x/y, da0 - da14, mrd, mwr t hbs (bus busy) bus idle t dbs t dhak t h (bs-d) t hhrq t suhrq bus release bus idle (bus busy) t hhrq t v (bs-d) t dhak hi-z bus arbitration timing (when bus is busy) clkin t suhrq bstb holdrq holdak x/y, da0 - da14, mrd, mwr (bus busy) bus busy t hbs t dhak t suhrq bus idle bus idle (bus busy) t hhrq t v (bs-d) t dhak bus release t hhrq t dbs t h (bs-d) hi-z
data sheet u12801ej4v0ds00 49 m m m m pd77110, 77111, 77112 m pd77110 serial interface timing requirements parameter symbol condition min. typ. max. unit sck cycle time t csc 60 ns sck high-/low-level width t wsc 25 ns sck rise/fall time t rtsc 20 ns soen setup time t susoe 5ns soen hold time t hsoe 10 ns sien setup time t susie 5ns sien hold time t hsie 10 ns si setup time t susi 5ns si hold time t hsi 10 ns switching characteristics parameter symbol condition min. typ. max. unit sorq output delay time t dsor 25 ns sorq hold time t hsor 0ns so output delay time t dso 25 ns so hold time t hso 0ns siak output delay time t dsia 25 ns siak hold time t hsia 0ns caution if noise is superimposed on the serial clock, the serial interface may be deadlocked. bear in mind the following points when designing your system: ? reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). ? shorten the wiring between the devices sck1 and sck2 pins, and clock supply source. ? do not cross the signal lines of the serial clock with any other signal lines. do not route the serial clock line in the vicinity of a line through which a high alternating current flows. ? supply the clock to the sck1 and sck2 pins of the device from the clock source on a one-to- one basis. do not supply clock to several devices from one clock source. ? exercise care that the serial clock does not overshoot or undershoot. in particular, make sure that the rising and falling of the serial clock waveform are clear. make sure that the serial clock rises and falls linearly. the serial clock must not bound. noise must not be superimposed on the serial clock. the serial clock must not rise or fall step-wise.
data sheet u12801ej4v0ds00 50 m m m m pd77110, 77111, 77112 m pd77110 serial output timing 1 sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t hso t dso t dso t hsoe t susoe t susoe t hsoe t dsor t wsc t wsc t csc t hsor t rfsc hi-z serial output timing 2 (during successive output) sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t dso t hsoe t susoe t dsor t wsc t wsc t csc t hsor t rfsc last t hso hi-z
data sheet u12801ej4v0ds00 51 m m m m pd77110, 77111, 77112 m pd77110 serial input timing 1 sck1, sck2 siak1 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t susie t hsie t susie t hsie t hsia t susi t hsi 1st 2nd t rfsc t rfsc 3rd serial input timing 2 (during successive input) sck1, sck2 siak1 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t susie t hsie t hsia t susi t hsi 1st 3rd t rfsc t rfsc last last? 2nd
data sheet u12801ej4v0ds00 52 m m m m pd77110, 77111, 77112 m pd77110 host interface timing requirements parameter symbol condition min. typ. max. unit hrd delay time t dhr 10 ns hrd width t whr 60 ns hcs, ha0, ha1, read hold time t hhcar 0ns hcs, ha0, ha1 line hold time t hhcaw 0ns hrd, hwr recovery time t rechs 60 ns hwr delay time t dhw 10 ns hwr width t whw 60 ns hwr hold time t hhdw 0ns hwr setup time t suhdw 10 ns switching characteristics parameter symbol condition min. typ. max. unit hre, hwe output delay time t dhe 25 ns hre, hwe hold time t hhe 25 ns hrd valid time t vhdr 25 ns hrd hold time t hhdr 0ns
data sheet u12801ej4v0ds00 53 m m m m pd77110, 77111, 77112 m pd77110 host read interface timing clkin hrd t dhe t hhdr t hhcar t rechs t vhdr t whr t dhr t hhe hcs, ha0, ha1 hd0 - hd7 hre hi-z hi-z host write interface timing clkin hwr t dhe t hhdw t hhcaw t rechs t whw t dhw t hhe hcs, ha0, ha1 hd0 - hd7 hwe t suhdw
data sheet u12801ej4v0ds00 54 m m m m pd77110, 77111, 77112 m pd77110 general-purpose i/o port timing requirements parameter symbol condition min. typ. max. unit port input setup time t supi 0ns port input hold time t hpi 10 ns switching characteristics parameter symbol condition min. typ. max. unit port output delay time t dpo 25 ns general-purpose i/o port timing clkin p0 - p3 (output) t dpo t hpi t supi p0 - p3 (input)
data sheet u12801ej4v0ds00 55 m m m m pd77110, 77111, 77112 m pd77110 debugging interface (jtag) timing requirements parameter symbol condition min. typ. max. unit tck cycle time t ctck 120 ns tck high-/low-level width t wtck 50 ns tck rise/fall time t rftck 20 ns tms, tdi setup time t sudi 20 ns tms, tdi hold time t hdi 20 ns input pin setup time t sujin 20 ns input pin hold time t hjin 20 ns trst setup time t sutrst 100 ns switching characteristics parameter symbol condition min. typ. max. unit tdo output delay time t ddo 20 ns output pin output delay time t djout 20 ns debugging interface timing t ctck t sutrst t wtck t wtck t rftck t rftck t sudi t hdi t ddo t sujin t hjin t djout valid valid valid valid tck trst tms, tdi tdo capture state update state remark for details of jtag, refer to ieee1149.1 .
data sheet u12801ej4v0ds00 56 m m m m pd77110, 77111, 77112 m pd77111, 77112 (2) m m m m pd77111, 77112 ac characteristics (t a = - - - - 40 to +85 c, with iv dd and ev dd within recommended operating condition range) clock timing requirements parameter symbol condition min. typ. max. unit 25 ns iv dd = 1.8 to 2.7 v 25 m 50 mns clkin cycle time note 1 t ccx pll lock range note 2 iv dd = 2.3 to 2.7 v 10 m 50 mns clkin high-level width t wcxh 12.5 ns clkin low-level width t wcxl 12.5 ns clkin rise/fall time t rfcx 5ns iv dd = 1.8 to 2.7 v 25 ns internal clock cycle time requirements note 3 t cc (r) iv dd = 2.3 to 2.7 v 13.3 ns notes 1. m: multiple, n: division ratio 2. this is the range in which the pll is locked (stably oscillates). input t ccx within this range. 3. input t ccx so that the value of (t ccx ? m n) satisfies this condition. switching characteristics parameter symbol condition min. typ. max. unit during normal operation t ccx n ? mns internal clock cycle note t cc in halt mode t ccx n ? m l ns clkout cycle time t cco t cc ns n = 1, or even number t ccx ? 2 - 3ns during normal operation n = odd number (other than 1) t ccx ? m - 3ns clkout width t wco in halt mode t ccx ? m n - 3 ns clkout rise/fall time t rfco 5ns iv dd = 1.8 to 2.7 v 20 ns clkout delay time t dco iv dd = 2.3 to 2.7 v 15 ns note m: multiple, n: division ratio, l: halt division ratio
data sheet u12801ej4v0ds00 57 m m m m pd77110, 77111, 77112 m pd77111, 77112 clock i/o timing internal clock clkin clkout t ccx t cc, t cc(r) t wcxh t wcxl t rfcx t rfcx t cco t dco t wco t wco t rfco t rfco
data sheet u12801ej4v0ds00 58 m m m m pd77110, 77111, 77112 m pd77111, 77112 reset, interrupt timing requirements parameter symbol condition min. typ. max. unit on power application note 1 , in stop mode 100 + 2048t ccx m s reset low-level width t w (rl) during normal operation, in halt mode 4t cc note 2 note 3 ns on power application note 4 4t ccx ns reset recovery time t rec (r) 4t cc note 2 ns wakeup low-level width t w (wakeupl) 100 m s int1 - int4 low-level width t w (intl) 3t cc note 2 ns int1 - int4 recovery time t rec (int) 3t cc ns notes 1. the value on power application is the time from when the supply voltages have reached iv dd = 1.8 v and ev dd = 2.7 v. a stable clock input is also required. 2. note that t cc is i (i = integer of 1 to 16) times that during normal operation in the halt mode. 3. if the low-level width of reset is greater than 1024t cc , the pll initialization mode is triggered. if there is no need to use the pll initialization mode, set the width to less than 1024t cc . 4. when the power is turned on, a recovery period of 4t ccx is necessary before inputting reset. reset timing reset t w(rl) t rec(r) wakeup timing wakeup t w (wakeupl) interrupt timing int1 - int4 t w(intl) t rec(int)
data sheet u12801ej4v0ds00 59 m m m m pd77110, 77111, 77112 m pd77111, 77112 external data memory access ( m m m m pd77112 only) timing requirements parameter symbol condition min. typ. max. unit read data setup time t suddrd 18 ns read data hold time t hddrd 0ns switching characteristics parameter symbol condition min. typ. max. unit address cycle time t rcda t cc + (t cc t cdw ) note ns address output hold time t hda 0ns mrd output delay time t ddr 5ns write data output valid time t vddwd 5ns write data output hold time t hddwd 0ns mwr output delay time t ddw 0 0.5 t cc ns mwr output hold time t hda 0ns mwr low-level width t wdwl t cc t cdw - 3 ns mwr high-level width t wdwh 0.5 t cc - 3ns note t cdw : number of data wait cycles
data sheet u12801ej4v0ds00 60 m m m m pd77110, 77111, 77112 m pd77111, 77112 external data memory access timing (read) da0 - da13 mrd x/y d0 - d15 t rcda t ddr t ddr t suddrd t hddrd external data memory access timing (write) da0 - da13 x/y mwr d0 - d15 t rcda t ddw t vddwd hi-z hi-z t vddwd t hddwd t wdwl t wdwh t hda t ddw
data sheet u12801ej4v0ds00 61 m m m m pd77110, 77111, 77112 m pd77111, 77112 bus arbitration ( m m m m pd77112 only) timing requirements parameter symbol condition min. typ. max. unit holdrq setup time t suhrq 0ns holdrq hold time t hhrq 0ns switching characteristics parameter symbol condition min. typ. max. unit bstb hold time t hbs 0ns bstb output delay time t dbs 20 ns holdak output delay time t dhak 18 ns data hold time during bus arbitration t h (bs-d) 25 ns data valid time during bus arbitration t v (bs-d) 25 ns
data sheet u12801ej4v0ds00 62 m m m m pd77110, 77111, 77112 m pd77111, 77112 bus arbitration timing (when bus is idle) clkin t suhrq bstb holdrq holdak x/y, da0 - da13, mrd, mwr t hbs (bus busy) bus idle t dbs t dhak t h (bs-d) t hhrq t suhrq bus release bus idle (bus busy) t hhrq t v (bs-d) t dhak hi-z bus arbitration timing (when bus is busy) clkin t suhrq bstb holdrq holdak x/y, da0 - da13, mrd, mwr (bus busy) bus busy t hbs t dhak t suhrq bus idle bus idle (bus busy) t hhrq t v (bs-d) t dhak bus release t hhrq t dbs t h (bs-d) hi-z
data sheet u12801ej4v0ds00 63 m m m m pd77110, 77111, 77112 m pd77111, 77112 serial interface timing requirements parameter symbol condition min. typ. max. unit sck cycle time t csc 60 ns sck high-/low-level width t wsc 25 ns sck rise/fall time t rfsc 20 ns iv dd = 1.8 to 2.7 v 10 ns soen setup time t susoe iv dd = 2.3 to 2.7 v 5 ns iv dd = 1.8 to 2.7 v 15 ns soen hold time t hsoe iv dd = 2.3 to 2.7 v 10 ns iv dd = 1.8 to 2.7 v 10 ns sien setup time t susie iv dd = 2.3 to 2.7 v 5 ns iv dd = 1.8 to 2.7 v 15 ns sien hold time t hsie iv dd = 2.3 to 2.7 v 10 ns iv dd = 1.8 to 2.7 v 10 ns si setup time t susi iv dd = 2.3 to 2.7 v 5 ns iv dd = 1.8 to 2.7 v 15 ns si hold time t hsi iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 1.8 to 2.7 v 30 ns sorq output delay time t dsor iv dd = 2.3 to 2.7 v 25 ns sorq hold time t hsor 0ns iv dd = 1.8 to 2.7 v 30 ns so output delay time t dso iv dd = 2.3 to 2.7 v 25 ns so hold time t hso 0ns iv dd = 1.8 to 2.7 v 30 ns siak output delay time t dsia iv dd = 2.3 to 2.7 v 25 ns siak hold time t hsia 0ns
data sheet u12801ej4v0ds00 64 m m m m pd77110, 77111, 77112 m pd77111, 77112 caution if noise is superimposed on the serial clock, the serial interface may be deadlocked. bear in mind the following points when designing your system: ? reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). ? shorten the wiring between the device's sck1 and sck2 pins, and clock supply source. ? do not cross the signal lines of the serial clock with any other signal lines. do not route the serial clock line in the vicinity of a line through which a high alternating current flows. ? supply the clock to the sck1 and sck2 pins of the device from the clock source on a one-to- one basis. do not supply clock to several devices from one clock source. ? exercise care that the serial clock does not overshoot or undershoot. in particular, make sure that the rising and falling of the serial clock waveform are clear. make sure that the serial clock rises and falls linearly. the serial clock must not bound. noise must not be superimposed on the serial clock. the serial clock must not rise or fall step-wise.
data sheet u12801ej4v0ds00 65 m m m m pd77110, 77111, 77112 m pd77111, 77112 serial output timing 1 sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t hso t dso t dso t hsoe t susoe t susoe t hsoe t dsor t wsc t wsc t csc t hsor t rfsc hi-z serial output timing 2 (during successive output) sck1, sck2 t rfsc sorq1 soen1, soen2 so1, so2 1st last t dso t hsoe t susoe t dsor t wsc t wsc t csc t hsor t rfsc last t hso
data sheet u12801ej4v0ds00 66 m m m m pd77110, 77111, 77112 m pd77111, 77112 serial input timing 1 sck1, sck2 siak1 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t susie t hsie t susie t hsie t hsia t susi t hsi 1st 2nd t rfsc t rfsc 3rd serial input timing 2 (during successive input) sck1, sck2 siak1 sien1, sien2 si1, si2 t csc t wsc t wsc t dsia t susie t hsie t hsia t susi t hsi 1st 3rd t rfsc t rfsc last last? 2nd
data sheet u12801ej4v0ds00 67 m m m m pd77110, 77111, 77112 m pd77111, 77112 host interface timing requirements parameter symbol condition min. typ. max. unit iv dd = 1.8 to 2.7 v 15 ns hrd delay time t dhr iv dd = 2.3 to 2.7 v 10 ns hrd width t whr 60 ns hcs, ha0, ha1, read hold time t hhcar 0ns hcs, ha0, ha1 line hold time t hhcaw 0ns hrd, hwr recovery time t rechs 60 ns iv dd = 1.8 to 2.7 v 15 ns hwr delay time t dhw iv dd = 2.3 to 2.7 v 10 ns hwr width t whw 60 ns hwr hold time t hhdw 0 ns iv dd = 1.8 to 2.7 v 15 ns hwr setup time t suhdw iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 1.8 to 2.7 v 30 ns hre, hwe output delay time t dhe iv dd = 2.3 to 2.7 v 25 ns iv dd = 1.8 to 2.7 v 30 ns hre, hwe hold time t hhe iv dd = 2.3 to 2.7 v 25 ns iv dd = 1.8 to 2.7 v 30 ns hrd valid time t vhdr iv dd = 2.3 to 2.7 v 25 ns hrd hold time t hhdr 0ns
data sheet u12801ej4v0ds00 68 m m m m pd77110, 77111, 77112 m pd77111, 77112 host read interface timing clkin hrd t dhe t hhdr t hhcar t rechs t vhdr t whr t dhr t hhe hcs, ha0, ha1 hd0 - hd7 hre hi-z hi-z host write interface timing clkin hwr t dhe t hhdw t hhcaw t rechs t whw t dhw t hhe hcs, ha0, ha1 hd0 - hd7 hwe t suhdw
data sheet u12801ej4v0ds00 69 m m m m pd77110, 77111, 77112 m pd77111, 77112 general-purpose i/o port timing requirements parameter symbol condition min. typ. max. unit port input setup time t supi 0ns iv dd = 1.8 to 2.7 v 15 ns port input hold time t hpi iv dd = 2.3 to 2.7 v 10 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 1.8 to 2.7 v 30 ns port output delay time t dpo iv dd = 2.3 to 2.7 v 25 ns general-purpose i/o port timing clkin p0 - p3 (output) t dpo t hpi t supi p0 - p3 (input)
data sheet u12801ej4v0ds00 70 m m m m pd77110, 77111, 77112 debugging interface (jtag) timing requirements parameter symbol condition min. typ. max. unit tck cycle time t ctck 120 ns tck high-/low-level width t wtck 50 ns tck rise/fall time t rftck 20 ns iv dd = 1.8 to 2.7 v 25 ns tms, tdi setup time t sudi iv dd = 2.3 to 2.7 v 20 ns iv dd = 1.8 to 2.7 v 25 ns tms, tdi hold time t hdi iv dd = 2.3 to 2.7 v 20 ns iv dd = 1.8 to 2.7 v 25 ns input pin setup time t sujin iv dd = 2.3 to 2.7 v 20 ns iv dd = 1.8 to 2.7 v 25 ns input pin hold time t hjin iv dd = 2.3 to 2.7 v 20 ns trst setup time t sutrst 100 ns switching characteristics parameter symbol condition min. typ. max. unit iv dd = 1.8 to 2.7 v 25 ns tdo output delay time t ddo iv dd = 2.3 to 2.7 v 20 ns iv dd = 1.8 to 2.7 v 25 ns output pin output delay time t djout iv dd = 2.3 to 2.7 v 20 ns
data sheet u12801ej4v0ds00 71 m m m m pd77110, 77111, 77112 debugging interface timing t ctck t wtck t sutrst t sudi t hdi t ddo t sujin t hjin valid valid t djout t wtck t rftck t rftck valid valid tck trst tms, tdi tdo capture state update state remark for details of jtag, refer to ieee1149.1 .
data sheet u12801ej4v0ds00 72 m m m m pd77110, 77111, 77112 11. package 100-pin plastic tqfp (fine pitch) (14x14) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.0 0.2 14.0 0.2 0.5 (t.p.) 1.0 j 16.0 0.2 k c 14.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 1.0 n p q 0.10 1.0 0.1 0.1 0.05 s100gc-50-9eu-2 s 1.27 max. h 0.22 + 0.05 - 0.04 m 0.145 + 0.055 - 0.045 r3 + 7 - 3 75 76 50 100 1 26 25 51 s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u12801ej4v0ds00 73 m m m m pd77110, 77111, 77112 60 41 40 21 61 80 120 80-pin plastic tqfp (fine pitch) (12x12) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 14.0 0.2 12.0 0.2 1.25 14.0 0.2 c 12.0 0.2 0.10 i j h 0.22 0.05 0.5 (t.p.) k 1.0 0.2 f 1.25 m 0.145 0.05 1.0 0.05 p q n 0.10 0.1 0.05 l 0.5 0.2 s80gk-50-9eu-1 s 1.2 max. r3 + 7 - 3 m s s n j detail of lead end c d a b r k m l p i s q g f h
data sheet u12801ej4v0ds00 74 m m m m pd77110, 77111, 77112 a s b 9 8 7 6 5 4 3 2 1 ja b c d e f g h 80-pin plastic fbga (9x9) item millimeters b c 8.40 8.40 d 9.00 0.10 a 9.00 0.10 s80f1-80-cn1-1 r25 w y1 0.20 0.20 e f 0.8 (t.p.) 1.30 h i 0.36 k 0.10 l m 0.08 p q r0.3 c1.0 0.96 g 0.35 0.1 j 1.31 0.15 0.50 f +0.05 ?.10 p index mark r j feg h i wsa wsb ks y1 s f m s m l d c a b q ab
data sheet u12801ej4v0ds00 75 m m m m pd77110, 77111, 77112 12. recommended soldering conditions it is recommended to solder this product under the following conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. surface mount type m m m m pd77110gc-9eu: 100-pin plastic tqfp (fine pitch) (14 14 mm) m m m m pd77111gk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12 mm) process conditions symbol infrared ray reflow package peak temperature: 235 c, time: 30 seconds max (210 c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 30 seconds max (210 c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 hours) vp15-103-2 partial heating method pin temperature: 300 c max, time: 3 seconds max (per side of device) - m m m m pd77112gc-xxx-9eu: 100-pin plastic tqfp (fine pitch) (14 14 mm) process conditions symbol infrared ray reflow package peak temperature: 235 c, time: 30 seconds max (210 c min), number of times: 3 max, number of days: 7 note (after that, prebaking is necessary for 10 hours) ir35-107-3 vps package peak temperature: 215 c, time: 30 seconds max (210 c min), number of times: 3 max, number of days: 7 note (after that, prebaking is necessary for 10 hours) vp15-107-3 partial heating method pin temperature: 300 c max, time: 3 seconds max (per side of device) - note number of days in storage after the dry pack has been opened. the storage conditions are at 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except partial heating method).
data sheet u12801ej4v0ds00 76 m m m m pd77110, 77111, 77112 m m m m pd77111f1-xxx-cn1: 80-pin plastic fine-pitch bga (9 9 mm) process conditions symbol infrared ray reflow package peak temperature: 230 c, time: 30 seconds max (210 c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 hours) ir30-103-2 vps package peak temperature: 215 c, time: 30 seconds max (210 c min), number of times: 2 max, number of days: 3 note (after that, prebaking is necessary for 10 hours) vp15-103-2 note number of days in storage after the dry pack has been opened. the storage conditions are at 25 c, 65% rh max. caution do not use two or more soldering methods in combination (except partial heating method).
data sheet u12801ej4v0ds00 77 m m m m pd77110, 77111, 77112 [memo]
data sheet u12801ej4v0ds00 78 m m m m pd77110, 77111, 77112 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet u12801ej4v0ds00 79 m m m m pd77110, 77111, 77112 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd77110, 77111, 77112 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed : m pd77110gc-9eu the customer must judge the need for license: m pd77111gk-xxx-9eu, m pd77111f1-xxx-cn1, m pd77112gc-xxx-9eu the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8


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